Overview of the MAX11040 24-Bit Simultaneous-Sampling, Sigma-Delta ADC

Abstract: This application note highlights the key features of the MAX11040 simultaneous-sampling sigma-delta ADC. The article will discuss 4-channel simultaneous sampling; the ability to program phase delays individually for each channel; cascading up to eight devices; and the operation of the active-low FAULT and OVERFLOW signals. Example test data, generated with device's evaluation (EV) kit, will be shown.

The MAX11040 integrates four 24-bit, sigma-delta ADCs to enable 4-channel simultaneous sampling. Unlike multiplexed-channel sigma-delta ADCs that do not maintain phase integrity, the MAX11040 not only records the phase information but also allows the user to program phase on individual channels.

Figure 1 shows same analog signal applied (zero phase delay) to all four ADC inputs, and the resulting sampled data.


Figure 1. The same sine-wave signal was applied to the four inputs of the MAX11040. Simultaneous outputs are shown at right.

Users can independently program phase delay for each ADC channel with a maximum of 333µs delay in 1.33µs steps. By programming phase delays into the ADC channels, the users can null out inherent phase delays caused by filters, delay lines, etc., in their signal path. The delay step size is also smaller than the data rate, thus allowing the user a resolution not available after acquisition.

Figure 2 shows the sampled output when zero phase delay is programmed and when varying phase delays are programmed. In both cases, all four inputs are tied to the same signal source.


Figure 2. The same sine-wave signal was applied to the four inputs of the MAX11040. Figure 2A shows the simultaneous output from the four channels when zero phase delay was programmed. Figure 2B shows the simultaneous output from the four channels when varying phase delays were programmed.

If four channels are not sufficient for an application, one can cascade up to eight MAX11040 devices together to enable 32 channels of simultaneous sampling. This feature is ideal for applications such as EEG that requires multiple simultaneous sampling channels for brain-wave monitoring.

Figure 3 shows the device setup

• The CASCOUT signal from first device is fed into CASCIN of the second device. The setup is similar for second device to the third and following devices. Finally, active-low DRDYOUT from the last device signals that the data is ready from all devices.
• The active-low CLKOUT signal from the first device is fed into active-low XIN of all the other devices.
• Active-low FAULT and active-low OVRFLW are in a wired-OR arrangement.

Figure 3. Diagram of the setup for cascading up to 8 MAX11040 devices.

The MAX11040 generates active-low OVERFLOW and active-low FAULT signals whenever the input goes above ±0.88% of V_REFor above 6V, respectively. This feature is important for generating an alarm on saturation or if the application needs overvoltage (OV) protection.

Figure 4 illustrates the process for a fast-moving input; Figure 5 illustrates the process for a slow-moving input. For the fast signals, the transition on the active-low OVERFLOW and FAULT signals is almost simultaneous. One should note that there is a latent period from when the signal crosses the threshold and before the active-low OVERFLOW and FAULT signals go low. There is a similar recovery time before the signals return high.


Figure 4. High-frequency analog input OV detection and recovery for a fast-moving input.


Figure 5. High-frequency analog input OV detection and recovery for a slow-moving input.

The following example data was generated with the MAX11040 EV kit.

Figure 6 shows the block diagram of two ADCs. The settings were programmed for various phase delays. An AC signal of 4V_P-Prunning at 120Hz was provided to the 8 inputs (four inputs for each device). The phase delay for each channel was programmed with the following codes:

CH1	0	0	0µs
CH2	36	36	46.88µs
CH3	2 × 36	72	93.75µs
CH4	3 × 36	108	140.62µs
CH1	4 × 36	144	187.50µs
CH2	5 × 36	180	234.38µs
CH3	6 × 36	216	281.25µs
CH4	7 × 36	252	328.12µs

Figure 6. Two MAX11040 ADCs are shown with the various phase delays applied to the signal.

Figures 7 and 8 show the captured data from the two MAX11040 devices in Figure 6. One can see that, although same signal was applied to all the inputs, the resulting waveform is out of phase due to the programmed phase delay.


More detailed /static/ic5/dianlu/image (PDF, 279KB)
Figure 7.The data that resulted from the dual ADC setup in Figure 6.


More detailed /static/ic5/dianlu/image (PDF, 269KB)
Figure 8. A zoomed-in view of Figure 7.

If a designer wants to use active-low OVERFLOW or active-low FAULT as interrupt signals, then either an external D flip flop or an internal latch is needed in the hardware. The signals will become latched when the active-low OVERFLOW or active-low FAULT goes low on the active-low SD pin. The interrupt controller can reset the signals by driving the active-low RD pin low (Figure 9).