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1CLR
1D
1CLK
1PRE
1Q
1Q
地
v
抄送
2CLR
2D
2CLK
2PRE
2Q
2Q
d 或 pw p组件
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描述/orderinginformation
sn74lvc74a-q1
dualpositive-边缘-triggeredd-typeflip-翻牌圈
WITHCLEARANDPRESET
SCES481B–AUGUST2003–REVISEDDECEMBER2005
•
qualificationinaccordancewithaec-q100
(1)
•
QualifiedforAutomotiveApplications
•
客户-specificconfigurationcontrolcan
besupportedalongwithmajor-变更
批准
•
ESDProtectionExceeds2000VPer
密耳-标准-883,method3015;exceeds200v
usingmachinemodel(c=200pf,右=0)
•
operatesfrom2vto3.6v
•
inputsacceptvoltagesto5.5v
•
maxt
pd
of5.2nsat3.3v
•
TypicalV
olp
(outputgroundbounce)&指示灯;0.8v
atV
抄送
=3.3v,t
一个
=25
°
c
•
TypicalV
OHV
(outputv
哦
下冲)>2vat
v
抄送
=3.3v,t
一个
=25
°
c
(1)contactfactoryfordetails.q100qualificationdataavailable
onrequest.
thesn74lvc74a-q1dualpositive-边缘-triggeredd-typeflip-flopisdesignedfor2.7-vto3.6-vv
抄送
操作.
alowlevelatthepreset(预)orclear(clr)inputssetsorresetstheoutputs,regardlessofthelevelsofthe
otherinputs.whenpreandclrareinactive(高),dataatthedata(d)inputmeetingthesetuptime
requirementsistransferredtotheoutputsonthepositive-goingedgeoftheclockpulse.clocktriggeringoccurs
atavoltagelevelandisnotdirectlyrelatedtotherisetimeoftheclockpulse.followingthehold-timeinterval,
dataatthedinputcanbechangedwithoutaffectingthelevelsattheoutputs.
inputscanbedrivenfromeither3.3-vor5-vdevices.thisfeatureallowstheuseofthisdeviceasatranslatorin
amixed3.3-v/5-vsystemenvironment.
ORDERINGINFORMATION
t
一个
包装
(1)
orderablepartnumbertop-sidemarking
SOIC–DReelof2500SN74LVC74AQDRQ1LVC74AQ
–40
°
Cto125
°
c
TSSOP–PWReelof2000SN74LVC74AQPWRQ1LVC74AQ
(1)packagedrawings,标准包装数量,thermaldata,符号化,andpcbdesignguidelinesareavailableat
www.ti.com/sc/包装.
pleasebeawarethatanimportantnoticeconcerningavailability,标准保修,anduseincriticalapplicationsoftexas
instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
productiondatainformationiscurrentasofpublicationdate.
copyright©2003–2005,texasinstrumentsincorporated
ProductsconformtospecificationsperthetermsoftheTexas
instrumentsstandardwarranty.productionprocessingdoesnot
必要包括测试所有参数.
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