ADS5275IPFPT_集成电路资料查询网

 
  
产品 预览
特点
应用程序
描述
10−Bit
adc
PLL
s/h
se rializer
1X ADCLK
6X ADCLK
IN1
p
ADCLK
IN1
n
OUT1
p
OUT1
n
10−Bit
adc
s/h se rializer
IN2
p
IN2
n
OUT2
p
OUT2
n
10−Bit
adc
s/h se rializer
IN3
p
IN3
n
OUT3
p
OUT3
n
LClk
p
LClk
n
广告clk
p
广告clk
n
10−Bit
adc
s/h
se rializer
IN4
p
IN4
n
OUT4
p
OUT4
n
10−Bit
adc
s/h se rializer
IN5
p
IN5
n
OUT5
p
OUT5
n
10−Bit
adc
s/h
se rializer
IN6
p
IN6
n
OUT6
p
OUT6
n
10−Bit
adc
s/h se rializer
IN7
p
IN7
n
OUT7
p
OUT7
n
10−Bit
adc
s/h
se rializer
reference?
IN8
p
IN8
n
参考
t
入点t/分机
v
c m
参考
B
OUT8
p
OUT8
n
右 egisters
SCLK
SDAT一个
cs
控制
reset
pd
ADS5275
SBAS300–JANUARY2004–REVISEDNOVEMBER2004
8-频道,10-有点,40mspsadc
withSerialLVDSInterface
theads5275providesinternalreferences,orcan
optionallybedrivenwithexternalreferences.最好
•
maximumsamplerate:40msps
performancecanbeachievedthroughtheinternal
•
10-bitresolution
referencemode.
•
NoMissingCodes
theads5275isavailableinapowerpadtqfp-80
•
powerdissipation:768mw
packageandarespecifiedovera-40
°
Cto+85
°
c
operatingrange.
•
CMOSTechnology
•
simultaneoussample-和-保持
•
60.5dbsnrat10mhzif
•
SerializedLVDSOutputsMeetorExceed
requirementsofansitia/eia-644-astandard
•
InternalandExternalReferences
•
3.3vdigital/模拟供应
•
tqfp-80powerpad™package
•
PortableUltrasoundSystems
•
TapeDrives
•
TestEquipment
theads5275isahigh-业绩,40msps,
8-频道,parallelanalog-至-digitalconverter(adc).
internalreferencesareprovided,simplifyingsystem
designrequirements.lowpowerconsumptionallows
forthehighestofsystemintegrationdensities.串行
lvds(低-voltagedifferentialsignaling)outputsre-
ducethenumberofinterfacelinesandpackagesize.
inlvds,anintegratedphaselockloopmultipliesthe
incomingadcsamplingclockbyafactorof6.这个
高-frequencylvdsclockisusedinthedata
serializationandtransmissionprocessandiscon-
vertedtoanLVDSsignalfortransmissioninparallel
withthedata.providingthisadditionallvdsclock
allowsforeasydelaymatching.thewordoutputof
eachinternalADCisserializedandtransmittedeither
msborlsbfirst.thebitfollowingtherisingedgeof
theadcclockoutputisthefirstbitoftheword.
pleasebeawarethatanimportantnoticeconcerningavailability,标准保修,anduseincriticalapplicationsoftexas
instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
powerpadisatrademarkoftexasinstruments.
allothertrademarksarethepropertyoftheirrespectiveowners.
productpreviewinformationconcernsproductsintheforma-
copyright©2004,texasinstrumentsincorporated
开发阶段.characteristicdataandother
规范设计目标.texasinstrumentsreservesthe
右更改或中断eseproductswithoutdotice.

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本平台电子爱好着纯手工中文简译:	截至2020/5/17日,支持英文词汇500个

     产品预览特点应用程序描述 10−Bit adc PLL s/h se rializer 1X ADCLK 6X ADCLK IN1 p ADCLK IN1 n OUT1 p OUT1 n 10−Bit adc s/h se rializer IN2 p IN2 n OUT2 p OUT2 n 10−Bit adc s/h se rializer IN3 p IN3 n OUT3 p OUT3 n LClk p LClk n 广告clk p 广告clk n 10−Bit adc s/h se rializer IN4 p IN4 n OUT4 p OUT4 n 10−Bit adc s/h se rializer IN5 p IN5 n OUT5 p OUT5 n 10−Bit adc s/h se rializer IN6 p IN6 n OUT6 p OUT6 n 10−Bit adc s/h se rializer IN7 p IN7 n OUT7 p OUT7 n 10−Bit adc s/h se rializer reference? IN8 p IN8 n 参考 t 入点t/分机 v c m 参考 B OUT8 p OUT8 n 右 egisters SCLK SDAT一个 cs 控制 reset pd ADS5275 SBAS300–JANUARY2004–REVISEDNOVEMBER2004 8-频道,10-有点,40mspsadc withSerialLVDSInterface theads5275providesinternalreferences,orcan optionallybedrivenwithexternalreferences.最好 • maximumsamplerate:40msps performancecanbeachievedthroughtheinternal • 10-bitresolution referencemode. • NoMissingCodes theads5275isavailableinapowerpadtqfp-80 • powerdissipation:768mw packageandarespecifiedovera-40 ° Cto+85 ° c operatingrange. • CMOSTechnology • simultaneoussample-和-保持 • 60.5dbsnrat10mhzif • SerializedLVDSOutputsMeetorExceed requirementsofansitia/eia-644-astandard • InternalandExternalReferences • 3.3vdigital/模拟供应 • tqfp-80powerpad™package • PortableUltrasoundSystems • TapeDrives • TestEquipment theads5275isahigh-业绩,40msps, 8-频道,parallelanalog-至-digitalconverter(adc). internalreferencesareprovided,simplifyingsystem designrequirements.lowpowerconsumptionallows forthehighestofsystemintegrationdensities.串行 lvds(低-voltagedifferentialsignaling)outputsre- ducethenumberofinterfacelinesandpackagesize. inlvds,anintegratedphaselockloopmultipliesthe incomingadcsamplingclockbyafactorof6.这个高-frequencylvdsclockisusedinthedata serializationandtransmissionprocessandiscon- vertedtoanLVDSsignalfortransmissioninparallel withthedata.providingthisadditionallvdsclock allowsforeasydelaymatching.thewordoutputof eachinternalADCisserializedandtransmittedeither msborlsbfirst.thebitfollowingtherisingedgeof theadcclockoutputisthefirstbitoftheword. pleasebeawarethatanimportantnoticeconcerningavailability,标准保修,anduseincriticalapplicationsoftexas instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. powerpadisatrademarkoftexasinstruments. allothertrademarksarethepropertyoftheirrespectiveowners. productpreviewinformationconcernsproductsintheforma- copyright©2004,texasinstrumentsincorporated 开发阶段.characteristicdataandother 规范设计目标.texasinstrumentsreservesthe 右更改或中断eseproductswithoutdotice.

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