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特性
产品
描述
TL16C2550
SLWS161–JUNE2005
2.5-vto5-vdualuartwith16-bytefifos
•
internaldiagnosticcapabilities:
•
programmableauto-rtsandauto-cts–loopbackcontrolsforcommunications
LinkFaultIsolation
•
inauto-ctsmode,ctscontrolstransmitter
–break,parity,overrun,andframingerror
•
inauto-rtsmode,rcvfifocontentsand
Simulation
ThresholdControlRTS
•
FullyPrioritizedInterruptSystemControls
•
SerialandModemControlOutputsDrivea
RJ11CableDirectlyWhenEquipmentIson
•
modemcontrolfunctions(cts,rts,dsr,
thesamepowerdropdtr,ri,anddcd)
•
CapableofRunningWithAllExisting
•
availablein48-pintqfp(pfb),44-pinplcc
tl16c450software(fn),or32-pinqfn(rhb)包装
•
afterreset,allregistersareidenticaltothe
•
pincompatiblewithtl16c752b(48-管脚
tl16c450registersetpackage)
•
upto24-mhzclockrateforupto1.5-mbaud
OperationWithV
CC
=5V
•
要点-的-saleterminals
•
upto20-mhzclockrateforupto1.25-mbaud
•
GamingTerminals
OperationWithV
CC
=3.3v
•
PortableApplications
•
upto16-mhzclockrateforupto1-mbaud
•
RouterControl
OperationWithV
CC
=2.5v
•
CellularData
•
inthetl16c450mode,holdandshift
•
FactoryAutomation
RegistersEliminatetheNeedforPrecise
SynchronizationBetweentheCPUandSerial
数据
•
ProgrammableBaudRateGeneratorAllows
TheTL16C2550isadualuniversalasynchronous
DivisionofAnyInputReferenceClockby1to
receiverandtransmitter(uart).itincorporatesthe
functionalityoftwotl16c550duarts,eachuart
(2
16
-1)andgeneratesaninternal16×clock
havingitsownregistersetandfifos.thetwo
•
StandardAsynchronousCommunicationBits
UARTsshareonlythedatabusinterfaceandclock
(开始,停止,andparity)addedtoordeleted
源,otherwisetheyoperateindependently.
FromtheSerialDataStream
AnothernamefortheuartfunctionisAsynchronous
•
5-v,3.3-v,and2.5-voperation
communicationselement(ace),andthesetermswill
beusedinterchangeably.thebulkofthisdocument
•
IndependentReceiverClockInput
willdescribethebehaviorofeachace,withthe
•
transmit,receive,linestatus,anddataset
understandingthattwosuchdevicesareincorporated
InterruptsIndependentlyControlled
intothetl16c2550.
•
FullyProgrammableSerialInterface
特性:
–5-,6-,7-,or8-bitcharacters
–even-,odd-,orno-paritybitgenerationand
发现
–1-,11/2-,or2-stopbitgeneration
–baudgeneration(dcto1mbit/s)
•
false-startbitdetection
•
CompleteStatusReportingCapabilities
•
3-stateoutputttldrivecapabilitiesfor
BidirectionalDataBusandControlBus
•
LineBreakGenerationandDetection
pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsoftexas
instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
productpreviewinformationconcernsproductsintheforma-
copyright©2005,texasinstrumentsincorporated
tiveordesignphaseofdevelopment.characteristicdataandother
specificationsaredesigngoals.texasinstrumentsreservesthe
righttochangeordiscontinuetheseproductswithoutnotice.
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