MOTOROLA
MC68HC681
用户’s 手工的
v
表格 的 内容
Paragraph 页
号码 标题 号码
部分 1
介绍
1.1 内部的 控制 逻辑 ...........................................................................1-4
1.2 定时 逻辑.........................................................................................1-4
1.3 中断 控制 逻辑..........................................................................1-5
1.4 数据 总线 缓存区....................................................................................1-5
1.5 交流 途径 一个 和 b ......................................................1-5
1.6 输入 端口..............................................................................................1-5
1.7 输出 端口...........................................................................................1-6
部分 2
信号 描述
2.1 V
CC
和 地 .......................................................................................2-2
2.2 结晶 输入 或者 外部 时钟 (x1)..................................................2-2
2.3 结晶 输入 (x2) .................................................................................2-3
2.4 重置 (重置
)..................................................................................2-3
2.5 碎片-选择 (cs
) ..................................................................................2-3
2.6 读/写 (r/w
) .................................................................................2-3
2.7 数据 转移 ackowledge (dtack
) ...................................................2-4
2.8 寄存器-选择 总线 (rs1–rs4) ..........................................................2-4
2.9 数据 总线 (d0–d7)................................................................................2-4
2.10 interupt 要求 (irq
).........................................................................2-4
2.11 interupt ackowledge (iack
).................................................................2-4
2.12 频道 一个/b 传输者 串行-数据 输出 (txda/txdb).................2-4
2.13 频道 一个/b 接受者 串行-数据 输入 (rxda/rxdb).......................2-4
2.14 并行的 输入 (ip0–ip5) ......................................................................2-4
2.14.1 IP0 ..............................................................................................2-4
2.14.2 IP1 ..............................................................................................2-5
2.14.3 IP2 ..............................................................................................2-5
2.14.4 IP3 ..............................................................................................2-5
2.14.5 IP4 ..............................................................................................2-5
2.14.6 IP5 ..............................................................................................2-5
2.15 并行的 输出 (op0–op7)................................................................2-5
2.15.1 OP0 ............................................................................................2-5
2.15.2 OP1 ............................................................................................2-5
2.15.3 OP2 ............................................................................................2-6
2.15.4 OP3 ............................................................................................2-6
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