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PARAMETERMEASUREMENTINFORMATION
SCLK
CS
(1)
DIN
DOUT
t
SCLK
t
CSSC
t
SPW
t
DIST
t
DIHD
t
SPW
t
CSDO
t
DOPD
t
DOHD
便条: (1) CS 能 是 系 低.
DRDY
DOUT
t
DRDY
t
DDO
ADS1258
SBAS297A–JUNE2005–REVISEDSEPTEMBER2005
figure1.serialinterfacetiming
SERIALINTERFACETIMINGCHARACTERISTICS
SYMBOLDESCRIPTIONMINMAXUNITS
t
SCLK
SCLKPeriod2
τ
CLK
(1)
t
SPW
sclkhighorlowpulsewidth(exceedingmaxresetsspiinterface)0.84096
(2)
τ
CLK
t
CSSC
cslowtofirstsclk:setuptime
(3)
0.5
τ
CLK
t
DIST
validdintosclkrisingedge:setuptime10ns
t
DIHD
validdintosclkrisingedge:holdtime5ns
t
DOPD
sclkfallingedgetovalidnewdout:propagationdelay
(4)
5ns
t
DOHD
sclkfallingedgetoolddoutinvalid:holdtime0ns
t
CSDO
cshightodoutinvalid(触发-状态)5
τ
CLK
(1)
τ
CLK
=masterclockperiod=1/f
CLK
.
(2)programmableto256
τ
CLK
.
(3)cscanbetiedlow.
(4)doutload=20pf||100k
Ω
todgnd.
figure2.drdyupdatetiming
DRDYUPDATETIMINGCHARACTERISTICS
SYMBOLDESCRIPTIONTYPUNITS
t
DRDY
DRDYHighPulseWidthWithoutDataRead1
τ
CLK
t
DDO
validdouttodrdyfallingedge(cs=0)0.5
τ
CLK
6
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