www.德州仪器.com
TMS320VC5409A
fixed-pointdigitalsignalprocessor
SPRS140F–NOVEMBER2000–REVISEDJANUARY2005
table2-2.signaldescriptions(持续)
终端
i/o
(1)
描述
名字
multichannelbufferedserialport0(mcbsp#0),multichannelbufferedserialport1(mcbsp#1),
andmultichannelbufferedserialport2(mcbsp#2)信号
BCLKR0
(2)
receiveclockinput.bclkrcanbeconfiguredasaninputoranoutput;itisconfiguredasaninput
BCLKR1
(2)
i/o/z
followingreset.bclkrservesastheserialshiftclockforthebufferedserialportreceiver.
BCLKR2
(2)
BDR0
BDR1ISerialdatareceiveinput
BDR2
BFSR0
framesynchronizationpulseforreceiveinput.bfsrcanbeconfiguredasaninputoranoutput;itis
bfsr1i/o/z
configuredasaninputfollowingreset.thebfsrpulseinitiatesthereceivedataprocessoverbdr.
BFSR2
BCLKX0
(2)
transmitclock.bclkxservesastheserialshiftclockforthemcbsptransmitter.bclkxcanbe
BCLKX1
(2)
i/o/zconfiguredasaninputoranoutput,andisconfiguredasaninputfollowingreset.bclkxentersthe
BCLKX2
(2)
高-impedancestatewhenoffgoeslow.
BDX0
serialdatatransmitoutput.bdxisplacedinthehigh-impedancestatewhennottransmitting,whenrsis
bdx1o/z
asserted,orwhenoffislow.
BDX2
bfsx0framesynchronizationpulsefortransmitinput/输出.thebfsxpulseinitiatesthedatatransmitprocess
bfsx1i/o/zoverbdx.bfsxcanbeconfiguredasaninputoranoutput,andisconfiguredasaninputfollowingreset.
bfsx2bfsxgoesintothehigh-impedancestatewhenoffislow.
host-portinterfacesignals
parallelbidirectionaldatabus.thehpidatabusisusedbyahostdevicebustoexchangeinformationwith
thehpiregisters.thesepinscanalsobeusedasgeneral-purposei/opins.hd0-hd7isplacedinthe
高-impedancestatewhennotoutputtingdataorwhenoffislow.thehpidatabusincludesbus
hd0-hd7
(2)(3)
i/o/zholderstoreducethestaticpowerdissipationcausedbyfloating,unusedpins.whenthehpidatabusis
notbeingdrivenbythe5409a,thebusholderskeepthepinsatthepreviouslogiclevel.thehpidatabus
holdersaredisabledatresetandcanbeenabled/disabledviathehbhbitofthebscr.thesepinsalso
haveschmitttriggerinputs.
controlinputs.hcntl0andhcntl1selectahostaccesstooneofthethreehpiregisters.thecontrol
HCNTL0
(4)
iinputshaveinternalpullupsthatareonlyenabledwhenhpiena=0.thesepinsarenotusedwhenhpi16
HCNTL1
(4)
=1.
byteidentification.hbilidentifiesthefirstorsecondbyteoftransfer.thehpilinputhasaninternalpullup
HBIL
(4)
I
resistorthatisonlyenabledwhenhpiena=0.thispinisnotusedwhenhpi16=1.
chipselect.hcsistheselectinputforthehpiandmustbedrivenlowduringaccesses.thechipselect
HCS
(2)(4)
I
inputhasaninternalpullupresistorthatisonlyenabledwhenhpiena=0.
HDS1
(2)(4)
datastrobe.hds1andhds2aredrivenbythehostreadandwritestrobestocontrolthetransfer.这
I
HDS2
(2)(4)
strobeinputshaveinternalpullupresistorsthatareonlyenabledwhenhpiena=0.
addressstrobe.hostwithmultiplexedaddressanddatapinsrequireshastolatchtheaddressinthe
有
(2)(4)
I
hpiaregister.hasinputhasaninternalpullupresistorthatisonlyenabledwhenhpiena=0.
读/写.hr/wcontrolsthedirectionofthehpitransfer.hr/whasaninternalpullupresistorthatis
hr/w
(4)
I
onlyenabledwhenhpiena=0.
readyoutput.hrdygoesintothehigh-impedancestatewhenoffislow.thereadyoutputinformsthe
hrdyo/z
hostwhenthehpiisreadyforthenexttransfer.
interruptoutput.thisoutputisusedtointerruptthehost.whenthedspisinreset,hintisdrivenhigh.
hinto/z
hintgoesintothehigh-impedancestatewhenoffislow.thispinisnotusedwhenhpi16=1.
hpimoduleselect.hpienamustbetiedtodv
DD
tohavehpiselected.ifhpienaisleftopenor
connectedtoground,thehpimoduleisnotselected,internalpullupforthehpiinputpinsareenabled,
HPIENA
(5)
I
andthehpidatabushasholdersset.hpienaisprovidedwithaninternalpulldownresistorthatisalways
起作用的.hpienaissampledwhenrsgoeshighandisignoreduntilrsgoeslowagain.
hpi16modeselection.thispinmustbetiedtodv
DD
toenablehpi16mode.thepinhasaninternal
HPI16
(5)
I
pulldownresistorwhichisalwaysactive.ifhpi16isleftopenordrivenlow,thehpi16modeisdisabled.
SUPPLYPINS
CV
SS
sground.dedicatedgroundforthecorecpu
CV
DD
S+V
DD
.dedicatedpowersupplyforthecorecpu
DV
SS
sground.dedicatedgroundfori/opins
(4)thispinhasaninternalpullupresistor.
(5)thispinhasaninternalpulldownresistor.
介绍
15
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