www.德州仪器.com
THEORYOFOPERATION
d/asection
_
+电阻 string
Ref+
Ref−
dac 寄存器
V
输出
50 k
50 k
V
REF
H
V
REF
L
70 k
V
输出
2
V
REF
L
(
V
REF
H
V
REF
L
)
D
1024
RESISTORSTRING
V
REF
H
To 输出
放大器
R
R R
R
V
REF
L
OutputAmplifier
I
2
CInterface
DAC6573
SLAS402–NOVEMBER2003
thearchitectureofthedac6573consistsofastringdacfollowedbyanoutputbufferamplifier.figure27
showsageneralizedblockdiagramofthedacarchitecture.
figure27.r-stringdacarchitecture
theinputcodingtothedac6573isunsignedbinary,whichgivestheidealoutputvoltageas:
whered=decimalequivalentofthebinarycodethatisloadedtothedacregister;itcanrangefrom0to1023.
theresistorstringsectionisshowninfigure28.itisbasicallyadivide-用-2resistor,followedbyastringof
电阻器,eachofvaluer.thecodeloadedintothedacregisterdeterminesatwhichnodeonthestringthe
voltageistappedofftobefedintotheoutputamplifierbyclosingoneoftheswitchesconnectingthestringtothe
放大器.becausethearchitectureconsistsofastringofresistors,itisspecifiedmonotonic.
figure28.typicalresistorstring
theoutputbufferisagain-的-2noninvertingamplifier,capableofgeneratingrail-至-railvoltagesonitsoutput,
whichgivesanoutputrangeof0VtoV
DD
.itiscapableofdrivingaloadof2k
Ω
inparallelwith1000pftognd.
thesourceandsinkcapabilitiesoftheoutputamplifiercanbeseeninthetypicalcurves.theslewrateis1v/µs
withahalf-scalesettlingtimeof7µswiththeoutputunloaded.
I
2
cisa2-wireserialinterfacedevelopedbyphilipssemiconductor(seei
2
c-busspecification,version2.1,
january2000).thebusconsistsofadataline(sda)andaclockline(scl)withpullupstructures.whenthebus
是
空闲
,bothsdaandscllinesarepulledhigh.allthei
2
c-compatibledevicesconnecttothei
2
Cbusthrough
opendraini/opins,sdaandscl.一个
主控
设备,usuallyamicrocontrolleroradigitalsignalprocessor,
controlsthebus.themasterisresponsibleforgeneratingthesclsignalanddeviceaddresses.themasteralso
generatesspecificconditionsthatindicatethestartandstopofdatatransfer.一个
从动装置
devicereceivesand/或者
transmitsdataonthebusundercontrolofthemasterdevice.
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