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TMS320VC5416
fixed-pointdigitalsignalprocessor
SPRS095O–MARCH1999–REVISEDJANUARY2005
ListofTables
2-1terminalassignmentsforthetms320vc5416ggu(144-pinbgapackage).........................................11
2-2signaldescriptions...............................................................................................................13
3-1standardon-chipromlayout...............................................................................................19
3-2processormodestatus(pmst)registerbitfields........................................................................22
3-3softwarewait-stateregister(swwsr)bitfields.........................................................................24
3-4softwarewait-statecontrolregister(swcr)bitfields..................................................................24
3-5bank-switchingcontrolregister(bscr)地方..............................................................................25
3-6busholdercontrolbits..........................................................................................................26
3-7samplerateinputclockselection...........................................................................................32
3-8clockmodesettingsatreset.................................................................................................33
3-9dmdsectionofthedmmcrnregister......................................................................................38
3-10dmareloadregisterselection...............................................................................................41
3-11dmainterrupts...................................................................................................................42
3-12dmasynchronizationevents..................................................................................................42
3-13dmachannelinterruptselection..............................................................................................43
3-14deviceidregister(csidr)位................................................................................................45
3-15cpumemory-mappedregisters................................................................................................45
3-16peripheralmemory-mappedregistersforeachdspsubsystem........................................................46
3-17mcbspcontrolregistersandsubaddresses.................................................................................47
3-18dmasubbankaddressedregisters...........................................................................................48
3-19interruptlocationsandpriorities................................................................................................50
5-1inputclockfrequencycharacteristics.........................................................................................56
5-2clockmodepinsettingsforthedivide-用-2andbydivide-用-4clockoptions.......................................57
5-3divide-用-2anddivide-用-4clockoptionstimingrequirements.......................................................57
5-4divide-用-2anddivide-用-4clockoptionsswitchingcharacteristics...................................................57
5-5multiply-用-nclockoptiontimingrequirements..........................................................................59
5-6multiply-用-nclockoptionswitchingcharacteristics......................................................................59
5-7memoryreadtimingrequirements..........................................................................................60
5-8memoryreadswitchingcharacteristics.....................................................................................60
5-9memorywriteswitchingcharacteristics.....................................................................................63
5-10i/oreadtimingrequirements................................................................................................64
5-11i/oreadswitchingcharacteristics...........................................................................................64
5-12i/owriteswitchingcharacteristics............................................................................................65
5-13readytimingrequirementsforexternallygeneratedwaitstates......................................................67
5-14readyswitchingcharacteristicsforexternallygeneratedwaitstates..................................................67
5-15holdandholdatimingrequirements....................................................................................72
5-16holdandholdaswitchingcharacteristics...............................................................................72
5-17reset,bio,中断,andmp/mctimingrequirements..................................................................74
5-18instructionacquisition(iaq)andinterruptacknowledge(iack)switchingcharacteristics...........................76
ListofTables
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