先进的 i/o 控制 和 motherboard glue 逻辑
数据手册
smsc/非-smsc 寄存器 sets (
rev. 02-27-04)
页 4
smsc lpc47m172
数据手册
表格 的 内容
lpc47m172 数据手册 修订 history .................................................................................................3
chapter 1
一般 description..............................................................................................................12
chapter 2
管脚 lay输出 ............................................................................................................................ 13
chapter 3
描述 的 pin 功能 ................................................................................................15
3.1
缓存区 名字Descriptions ..........................................................................................................................23
3.2
管脚 和 internal resistors .......................................................................................................................24
3.3
管脚 那 需要 external resistors.........................................................................................................24
3.4
default state 的管脚...................................................................................................................................25
chapter 4
块 图解 ...................................................................................................................... 29
chapter 5
电源 和 时钟 functionality.............................................................................................30
5.1
3 volt 运作 /5 volt 至lerance ............................................................................................................30
5.2
vcc power ................................................................................................................................................30
5.3
vtr 电源.................................................................................................................................................30
5.3.1
trickle 电源 functionality .................................................................................................................31
5.4
v5p0_stby电源 ....................................................................................................................................31
5.5
32.768 khz trickle 时钟 在放...................................................................................................................31
5.5.1
indication 的32KHZ时钟...................................................................................................................31
5.6
14.318 mhz clock input .............................................................................................................................32
5.7
内部的PWRGOOD...................................................................................................................................32
5.8
最大 current values...........................................................................................................................32
5.9
电源 管理 events (pme/sci) .....................................................................................................32
chapter 6
函数的 description..........................................................................................................33
6.1
超级的 i/o registers....................................................................................................................................33
6.2
host 处理器 在terface(lpc) .................................................................................................................34
6.3
lpc interface .............................................................................................................................................34
6.3.1
lpc 接口 signal 定义 ...........................................................................................................34
6.3.2
lpc cycles .........................................................................................................................................34
6.3.3
地方 definitions...................................................................................................................................34
6.3.4
NLFRAME用法................................................................................................................................35
6.3.5
i/o 读 和 write cycles..................................................................................................................35
6.3.6
dma 读 和 写 cycles ..............................................................................................................35
6.3.7
dma protocol......................................................................................................................................35
6.3.8
电源 management............................................................................................................................36
6.3.9
同步 protocol....................................................................................................................................36
6.3.10
i/o 和 dma 星t fields.............................................................................................................37
6.3.11
lpc transfers .................................................................................................................................37
6.4
floppy disk controller ................................................................................................................................38
6.4.1
fdc configurati在 registers ..............................................................................................................38
6.4.2
fdc 内部的Registers........................................................................................................................38
6.4.3
状态 register 一个 (sra) .....................................................................................................................39
6.4.4
状态 register b (srb) .....................................................................................................................40
6.4.5
数字的 输出 register(dor).............................................................................................................42
6.4.6
录音带 驱动 register(tdr) .................................................................................................................43
6.4.7
数据 比率 选择寄存器(dsr)........................................................................................................44
6.4.8
主要的 状态Register...........................................................................................................................46
6.4.9
数据 register (先进先出)...........................................................................................................................47
6.4.10
数字的 输入 register(dir)..............................................................................................................48
6.4.11
配置控制 register(ccr) .............................................................................................49
6.4.12
状态 register encoding ................................................................................................................50
6.5
模式 的 operation....................................................................................................................................52
6.5.1
pc/在模式 .......................................................................................................................................52
6.5.2
ps/2 mode ..........................................................................................................................................52
6.5.3
模型 30模式 ...................................................................................................................................52
6.6
dma transfers ...........................................................................................................................................52
6.7
控制阶段.......................................................................................................................................53
6.7.1
Command阶段 ................................................................................................................................53
6.7.2
执行阶段 .................................................................................................................................53
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