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产品 预告(展)
NC −非 内部的 连接
14 15
重置
DTRB
DTRA
RTSA
OPA
RXRDYA
INTA
INTB
A0
A1
A2
NC
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
D5
D6
D7
RXB
RXA
TXRDYB
TXA
TXB
OPB
CSA
CSB
NC
17 18 19 20
pfb pACKAGE
(t运算 视图)
RA
CDA
DSRA
CTSA
47 46 45 44 4348 42
D4
D3
D2
D1
D0
TXRDYA
RTSB
CTSB
NC
IOW
CDB
地
IOR
DSRB
RIB
40 39 3841
21
22 23 24
37
13
XTAL1
NC
V
CC
XTAL2
RXRDYB
TL16C2550PFB
重置
OPA
D5
D6
A0
A2
A1
INTB
INTA
RXRDYA
RTSA
DTRA
DTRB
39
35
31
29
30
32
33
34
36
37
38
246 1 42 4041434435
7
8
9
10
11
12
13
14
15
16
17
1918 26 2820 21 22 23 24 25 27
RXB
RXA
TXRDYB
TXA
TXB
OPB
CSA
CSB
D7
IOW
XTAL1
XTAL2
CDB
地
RXRDYB
IOR
DSRB
RIB
RTSB
CTSB
D4
D0
CDA
CTSA
DSRA
RIA
V
CC
TXRDYA
D1
D2
D3
TL16C2550FN
fn pACKAGE
(t运算 视图)
TL16C2550
SLWS161–JUNE2005
EachACEisaspeedandvoltagerangeupgradeof
thetl16c550c,whichinturnisafunctionalupgrade
ofthetl16c450.functionallyequivalenttothe
tl16c450onpoweruporreset(singlecharacteror
tl16c450mode),eachacecanbeplacedinan
alternatefifomode.thisrelievesthecpuof
excessivesoftwareoverheadbybufferingreceived
andtobetransmittedcharacters.eachreceiverand
transmitterstoreupto16bytesintheirrespective
fifos,withthereceivefifoincludingthreead-
ditionalbitsperbyteforerrorstatus.inthefifo
模式,aselectableautoflowcontrolfeaturecan
significantlyreducesoftwareoverloadandincrease
systemefficiencybyautomaticallycontrollingserial
dataflowusinghandshakesbetweentheRTS#
outputandcts#input,thuseliminatingoverrunsin
thereceivefifo.
eachaceperformsserial-至-parallelconversionson
datareceivedfromaperipheraldeviceormodemand
storestheparalleldatainitsreceivebufferorfifo,
andeachaceperformsparallel-至-serialconversions
ondatasentfromitsCPUafterstoringtheparallel
datainitstransmitbufferorfifo.thecpucanread
thestatusofeitheraceatanytime.eachace
includescompletemodemcontrolcapabilityanda
processorinterruptsystemthatcanbetailoredtothe
应用.
eachaceincludesaprogrammablebaudrategener-
atorcapableofdividingareferenceclockwithdiv-
isorsoffrom1to65535,thusproducinga16×
internalreferenceclockforthetransmitterandre-
ceiverlogic.eachaceaccommodatesuptoa
1.5-mbaudserialdatarate(24-mhzinputclock).asa
referencepoint,thatspeedwouldgeneratea667-ns
bittimeanda6.7-µscharactertime(for8,n,1serial
数据),withtheinternalclockrunningat24mhz.
EachACEhasaTXRDY#andRXRDY#outputthat
canbeusedtointerfacetoadmacontroller.
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