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TIMINGREQUIREMENTS
t
h1
2.4 v
MCLK
重置
2.4 v
t
su1
2.4 v
t
wL
t
wH
t
d1
t
d2
t
d1
t
d2
t
en
t
d3
t
dis
t
su2
t
h2
D15
D15
SCLK
FS
FSD
DOUT
DIN
tlv320aic20,tlv320aic21
tlv320aic24,tlv320aic25
tlv320aic20k,tlv320aic24k
SLAS363D–MARCH2002–REVISEDAPRIL2005
figure1.hardwareresettiming
figure2.serialcommunicationtiming
TESTCONDITIONSMINTYPMAXUNIT
t
wH
pulseduration,mclkhigh5
t
wL
pulseduration,mclklow5
t
su1
setuptime,重置,beforemclkhigh(看Figure1)3
t
h1
holdtime,重置,aftermclkhigh(看Figure1)2
t
d1
delaytime,sclk
↑
tofs/fsd
↓
C
L
=20pF5ns
t
d2
delaytime,sclk
↑
tofs/fsd
↑
5
t
d3
delaytime,sclk
↑
toDOUT15
t
en
enabletime,sclk
↑
toDOUT15
t
dis
disabletime,sclk
↑
toDOUT15
t
su2
setuptime,din,beforesclk
↓
10
t
h2
holdtime,din,aftersclk
↓
10
14