cy7c63000/cy7c63001
cy7c63100/cy7c63101
cy7c63200/cy7c63201
初步的
5
.
管脚配置 (顶 视图)
逻辑 块 图解
6311–1
USB
d+,d–
端口
p0.0–p0.7
中断
控制 0
端口
p1.0–p1.7
1
8-位
RISC
OSC
内存
128 字节
非易失存储器
2k/4k 字节
1
2
3
4
5
6
7
9
13
14
15
16
17
18
20
19
p0.0
p0.1
p0.2
p0.3
p1.0
p1.2
VSS
CEXT
p0.4
p1.1
p0.6
p0.7
D+
p1.3
d-
VCC
插件/soic/
12
p0.5
8
VPP
XTALIN
XTALOUT
10
11
核心
电源
8-位
计时器
在 重置
Engine
Watch
Timer
1
2
3
4
5
6
7
9
11
12
13
14
15
16
18
17
p0.0
p0.1
p0.2
p0.3
p1.0
VSS
VPP
XTALIN
p0.4
p1.1
p0.6
p0.7
d-
D+
VCC
XTALOUT
插件/
10
p0.5
8
CEXT
Dog
6 mhz
共振器
1
2
3
4
5
6
9
11
15
16
17
18
19
20
22
21
p0.0
p0.1
p0.2
p0.3
p1.0
p1.2
VSS
CEXT
p0.6
p1.5
p1.1
p1.3
D+
p1.7
D–
VCC
24-管脚
14
p0.7
10
VPP
XTALIN
XTALOUT
12
13
7
8
p1.4
p1.6
24
23
p0.4
p0.5
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
instant-在
now<tm>
r/c
EXT
V
CC
/v
SS
soic/
20-管脚18-管脚
windowed cerdip
windowed cerdip windowed cerdip
: 点此下载
