www.德州仪器.com
1
2F
CLK2
0.5 ns
DAC5687
SLWS164B–FEBRUARY2005–REVISEDJUNE2005
electricalcharacteristics(digitalspecifications)(持续)
overrecommendedoperatingfree-airtemperaturerange,avdd=3.3v,clkvdd=3.3v,pllvdd=3.3v,iovdd=3.3v,
dvdd=1.8v,iout
FS
=19.2ma(unlessotherwisenoted)
DIGITALSPECIFICATIONS
PARAMETERTESTCONDITIONSMINTYPMAXUNIT
PLL
at600-khzoffset,measuredatdacoutput,
25mhz0-dbfstone,f
数据
=125msps,133dbc/hz
4xinterpolation,pll_freq=1,pll_kv=0
Phasenoise
at6-mhzoffset,measuredatdacoutput,
25mhz0-dbfstone,125msps,148.5dbc/hz
4xinterpolation,pll_freq=1,pll_kv=0
pll_freq=0,pll_kv=0370
pll_freq=0,pll_kv=1480
VCOmaximumfrequencyMHz
pll_freq=1,pll_kv=0495
pll_freq=1,pll_kv=1520
pll_freq=0,pll_kv=0225
pll_freq=0,pll_kv=1200
VCOminimumfrequencyMHz
pll_freq=1,pll_kv=0480
pll_freq=1,pll_kv=1480
NCOandQMCBLOCKS
QMCclockrate320MHz
NCOclockrate320MHz
SERIALPORTTIMING
t
s(sdenb)
setuptime,sdenbtorisingedgeofsclk20ns
setuptime,sdiovalidtorisingedgeof
t
s(sdio)
10ns
SCLK
holdtime,sdiovalidtorisingedgeof
t
h(sdio)
5ns
SCLK
t
SCLK
PeriodofSCLK100ns
t
SCLKH
HightimeofSCLK40ns
t
SCLK
LowtimeofSCLK40ns
t
d(数据)
DataoutputdelayafterfallingedgeofSCLK10ns
clockinput(clk1/clk1c,clk2/clk2c)
Dutycycle40%60%
differentialvoltage0.41v
timingparalleldatainput:clk1latchingmodes
(pllmode–Figure45,dualclockmodefifodisabled–seeFigure47,dualclockmodewithfifoenabled–seeFigure48)
setuptime,datavalidtorisingedgeof
t
s(数据)
0.5ns
CLK1
holdtime,datavalidafterrisingedgeof
t
h(数据)
1.5ns
CLK1
MaximumoffsetbetweenCLK1andCLK2
t_alignrisingedges–dualclockmodewithfifons
无能
timingparalleldatainput(externalclockmode,latchonplllockrisingedge,clk2clockinput,看Figure43)
setuptime,datavalidtorisingedgeof
t
s(数据)
72-
Ω
loadonplllock0.5ns
PLLLOCK
holdtime,datavalidafterrisingedgeof
t
h(数据)
72-
Ω
loadonplllock1.5ns
PLLLOCK
delayfromclk2risingedgetoplllock72-
Ω
loadonplllock.notethatplllock
t
延迟(plllock)
4.5ns
risingedgedelayincreaseswithalowerimpedanceload.
timingparalleldatainput(externalclockmode,latchonplllockfallingedge,clk2clockinput,看Figure44)
setuptime,datavalidtofallingedgeof
t
s(数据)
highimpedanceloadonplllock0.5ns
PLLLOCK
holdtime,datavalidafterfallingedgeof
t
h(数据)
highimpedanceloadonplllock1.5ns
PLLLOCK
10
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