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DAC5687
SLWS164B–FEBRUARY2005–REVISEDJUNE2005
terminalfunctions(持续)
终端
i/odescription
nameno.
inpllclockmodeanddualclockmodes,providesdatainputrateclock.inexternalclockmode,
clk159iprovidesoptionalinputdatarateclocktofifolatch.whenthefifoisdisabled,clk1isnotused
andcanbeleftunconnected.
clk1c60icomplementaryinputofclk1.
externalanddualclockmodeclockinput.inpllmode,clk2isunusedandcanbeleft
CLK262I
unconnected.
clk2c63icomplementaryofclk2.inpllmode,clk2cisunusedandcanbeleftunconnected.
clkgnd58,64igroundreturnforinternalclockbuffer
CLKVDD61IInternalclockbuffersupplyvoltage
34-36,39-43,一个-channeldatabits0through15.da15ismostsignificantdatabit(msb).da0isleastsignificant
da[15..0]i
48-55databit(lsb).ordercanbereversedbyregisterchange.
71-78,83-87,b-channeldatabits0through15.db15ismostsignificantdatabit(msb).db0isleastsignificant
db[0..15]i
90-92databit(lsb).ordercanbereversedbyregisterchange.
27,38,45,57,
dgnd69,81,88,93,idigitalgroundreturn
99
26,32,37,44,
dvdd56,68,82,89,idigitalsupplyvoltage
100
usedasexternalreferenceinputwheninternalreferenceisdisabled(i.e.,extloconnectedto
extio11i/oavdd).usedasinternalreferenceoutputwhenextlo=agnd,requiresa0.1-µfdecoupling
capacitortoAGNDwhenusedasreferenceoutput
内部的/externalreferenceselect.internalreferenceselectedwhentiedtoagnd,外部
extlo15i/oreferenceselectedwhentiedtoavdd.outputonlywhenatestisnotzero(register0x1bbits7
to3).
iouta121oa-channeldaccurrentoutput.fullscalewhenallinputbitsareset1
iouta220oa-channeldaccomplementarycurrentoutput.fullscalewhenallinputbitsare0
ioutb15ob-channeldaccurrentoutput.fullscalewhenallinputbitsareset1
ioutb26ob-channeldaccomplementarycurrentoutput.fullscalewhenallinputbitsare0
iognd47,79idigitali/ogroundreturn
iovdd46,80idigitali/osupplyvoltage
LPF66IPLLloopfilterconnection
synchronizationinputsignalthatcanbeusedtoinitializethenco,coursemixer,internalclock
PHSTR94I
分隔物,和/orfifocircuits.
PLLGND65IGroundreturnforinternalPLL
pllvdd67ipllsupplyvoltage.whenpllvddis0v,thepllisdisabled.
inpllmode,providesplllockstatusbitorinternalclocksignal.pllislockedtoinputclock
PLLLOCK70O
whenhigh.inexternalclockmode,providesinputrateclock.
whenqflagregisteris1,theqflagpinisusedbytheuserduringinterleaveddatainputmodeto
QFLAG98I
identifythebsample.highqflagindicatesbsample.mustberepeatedeverybsample.
resetb95iresetsthechipwhenlow.internalpull-向上
SCLK29ISerialinterfaceclock
sdenb28iactivelowserialdataenable,alwaysaninputtothedac5687
bidirectionalserialdatain3-pininterfacemode,inputonlyin4pininterfacemode.三-pinmode
sdio30i/o
isthedefaultafterchipreset.
serialinterfacedata,uni-directionaldataoutput,ifsdioisaninput.sdois3-statedwhenthe
SDO31O
3-pininterfacemodeisselected(register0x08bit1).
sleep96iasynchronoushardwarepowerdowninput.activehigh.internalpulldown.
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