www.国家的.com 6 修订 3.0
Geode™ SC2200
表格 的 内容
(持续)
4.5.3 RTCRegisters .....................................................120
4.5.3.1 UsageHints.....................................................124
4.5.4 rtcgeneral-purposerammap.......................................124
4.6 systemwakeupcontrol(swc) .........................................125
4.6.1 EventDetection ....................................................125
4.6.1.1 AudioCodecEvent ...............................................125
4.6.1.2 CEIRAddress ...................................................125
4.6.2 swcregisters.....................................................126
4.7 进入.businterface ..................................................130
4.7.1 datatransactions...................................................130
4.7.2 StartandStopConditions ............................................130
4.7.3 acknowledge(ack)循环 ............................................131
4.7.4 acknowledgeaftereverybyterule.....................................132
4.7.5 AddressingTransferFormats ..........................................132
4.7.6 ArbitrationontheBus................................................132
4.7.7 MasterMode ......................................................132
4.7.7.1 MasterStop .....................................................133
4.7.8 SlaveMode .......................................................134
4.7.9 配置 ......................................................134
4.7.10 ACBRegisters .....................................................135
4.8 LEGACY 函数的 BLOCKS .............................................138
4.8.1 ParallelPort .......................................................138
4.8.1.1 parallelportregisterandbitmaps...................................138
4.8.2 uartfunctionality(sp1andsp2) .....................................140
4.8.2.1 UARTModeRegisterBankOverview .................................140
4.8.2.2 SP1 和 SP2 寄存器 和 位 Maps 为 UART 符合实际 . . . . . . . . . . . . . . . 140
4.8.3 IR Communications Port (ircp) / 串行 端口 3 (sp3) 符合实际 . . . . . . . . . . . . 144
4.8.3.1 ir/sp3moderegisterbankoverview ................................144
4.8.3.2 ircp/sp3registerandbitmaps ....................................144
5.0 核心 逻辑 单元 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.1 FEATURELIST ...........................................................150
5.2 单元 ARCHITECTURE . . . . . .............................................151
5.2.1 快-pciinterfacetoexternalpcibus ..................................152
5.2.1.1 ProcessorMasteredCycles ........................................152
5.2.1.2 ExternalPCIMasteredCycles ......................................152
5.2.1.3 corelogicinternalorsub-isamasteredcycles ........................152
5.2.1.4 ExternalPCIBus.................................................152
5.2.1.5 BusMasterRequestPriority ........................................152
5.2.2 PSERIALInterface ..................................................152
5.2.2.1 VideoRetraceInterrupt ............................................152
5.2.3 IDEController......................................................153
5.2.3.1 IDEConfigurationRegisters ........................................153
5.2.3.2 PIOMode ......................................................153
5.2.3.3 BusMasterMode ................................................154
5.2.3.4 ultradma/33mode ...............................................155
5.2.4 UniversalSerialBus .................................................156
5.2.5 sub-isabusinterface ...............................................156
5.2.5.1 sub-isabuscycles ..............................................157
5.2.5.2 sub-isasupportofdelayedpcitransactions ..........................157
5.2.5.3 sub-isabusdatasteering.........................................158
5.2.5.4 i/orecoverydelays ..............................................158
5.2.5.5 ISADMA .......................................................159
5.2.5.6 ROMInterface ...................................................160
5.2.5.7 pciandsub-isasignalcyclemultiplexing ............................160