首页 | 最新需求 | 最新现货 | IC库存 | 供应商 | IC英文资料库 | IC中文资料库 | IC价格 | 电路图 | 应用资料 | 技术资料
 IC型号:
您现在的位置:首页 >  IC英文资料库 进入手机版 
 
资料编号:1091229
 
资料名称:TX49/H2 Core Architecture
 
文件大小: 1967318K
   
说明
 
介绍:
TX System RISC TX49 Family (64-bit RISC Processors)
 
 


: 点此下载
  浏览型号TX49/H2 Core Architecture的Datasheet PDF文件第1页
1
浏览型号TX49/H2 Core Architecture的Datasheet PDF文件第2页
2
浏览型号TX49/H2 Core Architecture的Datasheet PDF文件第3页
3
浏览型号TX49/H2 Core Architecture的Datasheet PDF文件第4页
4

5
浏览型号TX49/H2 Core Architecture的Datasheet PDF文件第6页
6
浏览型号TX49/H2 Core Architecture的Datasheet PDF文件第7页
7
浏览型号TX49/H2 Core Architecture的Datasheet PDF文件第8页
8
浏览型号TX49/H2 Core Architecture的Datasheet PDF文件第9页
9
 
本平台电子爱好着纯手工中文简译:截至2020/5/17日,支持英文词汇500个
内容
i
内容
处理 预防措施
1. 介绍 ........................................................................................................................................... 1-1
2. 特性................................................................................................................................................... 2-1
3. tx49 块 图解 ............................................................................................................................. 3-1
4. cpu 寄存器 overview....................................................................................................................... 4-1
4.1 介绍 ................................................................................................................................... 4-1
4.2 cpu 寄存器................................................................................................................................ 4-1
4.3 cp0 寄存器................................................................................................................................. 4-2
5. cpu 操作指南 设置 summary ............................................................................................................ 5-1
5.1 介绍 ................................................................................................................................... 5-1
5.2 操作指南 format........................................................................................................................ 5-1
5.3 操作指南 设置 overview.............................................................................................................. 5-2
5.3.1 加载 和 store 说明 (表格 5-1) .............................................................................. 5-2
5.3.2 computational 说明 (表格 5-2)............................................................................... 5-3
5.3.3 jump 和 branch 说明 (表格 5-3).......................................................................... 5-4
5.3.4 特定的 说明 (表格 5-4)............................................................................................ 5-5
5.3.5 例外 说明 (表格 5-5) ....................................................................................... 5-5
5.3.6 coprocessor 说明 (表格 5-6).................................................................................... 5-6
5.3.7 cp0 说明 (表格 5-7)................................................................................................. 5-6
5.3.8 乘以 和 分隔 说明 (表格 5-8)...................................................................... 5-7
5.3.9 debug 说明 (表格 5-9).............................................................................................5-7
5.3.10 其它 说明 (表格 5-10)............................................................................................ 5-7
5.4 操作指南 执行 循环........................................................................................................ 5-7
5.5 defining 进入 类型................................................................................................................... 5-8
6. cpu pipeline ......................................................................................................................................... 6-1
6.1 介绍 ................................................................................................................................... 6-1
6.2 基本 pipeline 运作............................................................................................................... 6-1
6.3 tx49 pipeline activities................................................................................................................ 6-2
6.4 branch 和 加载 延迟................................................................................................................. 6-3
6.4.1 delayed 加载........................................................................................................................... 6-3
6.4.2 delayed branching................................................................................................................. 6-3
6.5 非-blocking 加载 函数......................................................................................................... 6-4
6.6 interlock 和 例外 处理 ............................................................................................... 6-4
6.6.1 overview 的 interlock 和 例外 处理 .................................................................. 6-4
6.6.2 例外 情况............................................................................................................. 6-6
6.6.3 stall 情况 ..................................................................................................................... 6-6
6.6.4 外部 stalls....................................................................................................................... 6-6
6.6.5 interlock 和 例外 定时........................................................................................... 6-6
6.7 乘以 和 乘以/增加 说明 (mult, multu, madd, maddu)......................... 6-7
6.8 分隔 说明 (div, divu).................................................................................................. 6-7
6.9 streaming....................................................................................................................................... 6-7
7. 系统 控制 coprocessor, cp0 ........................................................................................................ 7-1
7.1 介绍 ................................................................................................................................... 7-1
7.2 cp0 寄存器................................................................................................................................. 7-2
7.2.1 index 寄存器 (reg
#
0)........................................................................................................... 7-2
7.2.2 随机的 寄存器 (reg
#
1)....................................................................................................... 7-3
7.2.3 entrylo0 寄存器 (reg
#
2) 和 entrylo1 寄存器 (reg
#
3)................................................. 7-4
7.2.4 context 寄存器 (reg
#
4) ....................................................................................................... 7-5
7.2.5 pagemask 寄存器 (reg
#
5) .................................................................................................. 7-6
7.2.6 连线的 寄存器 (reg
#
6) ......................................................................................................... 7-7
7.2.7 badvaddr 寄存器 (reg
#
8).................................................................................................. 7-8
7.2.8 计数 寄存器 (reg
#
9) ......................................................................................................... 7-9
7.2.9 entryhi 寄存器 (reg
#
10).................................................................................................. 7-10
资料评论区:
点击回复标题作者最后回复时间

标 题:
内 容:
用户名:
手机号:    (*未登录用户需填写手机号,手机号不公开,可用于网站积分.)
      
关于我们 | 联系我们
电    话13410210660             QQ : 84325569   点击这里与集成电路资料查询网联系
联系方式: E-mail:CaiZH01@163.com