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tlv320aic12,tlv320aic13
tlv320aic14,tlv320aic15
tlv320aic12k,tlv320aic14k
SLWS115D–OCTOBER2001–REVISEDSEPTEMBER2005
terminalfunctions(持续)
终端
i/odescription
nameaic12/13/12kaic14/15/14k
非.非.
programmablevirtualgroundfortheoutputofoutp2andoutp3(seethe
OUTMV14–O
registermap).
analogoutputnumber3fromthe16-
Ω
驱动器.thisoutputcandrivea
OUTP315–Omaximumloadof16
Ω
,andalsobeconfiguredaseithersingle-endedoutput
ordifferentialoutputbythecontrolregister6.
AVSS1616IAnalogground
AVDD1717IAnalogpowersupply
micin1818imicpreamplifierinput.itmustbeconnectedtoavssifnotused.
inp21919inoninvertinganaloginput2.itmustbeconnectedtoavssifnotused.
inm22020iinvertinganaloginput2.itmustbeconnectedtoavssifnotused.
biasoutputvoltageissoftwareselectablebetween1.35vand2.35v.它的
BIAS2121O
outputcurrentis5ma.
inm12222iinvertinganaloginput1.itmustbeconnectedtoavssifnotused.
inp12323inoninvertinganaloginput1.itmustbeconnectedtoavssifnotused.
hardwarereset.theresetfunctionisprovidedtoinitializealloftheinternal
reset2424iregisterstotheirdefaultvalues.theserialportisconfiguredtothedefault
stateaccordingly.
masterclock.mclkderivestheinternalclocksofthesigma-deltaanalog
MCLK2525I
interfacecircuit.
scl2626iprogrammablehostport(i
2
CorS
2
c)clockinput.
sda2727i/oprogrammablehostport(i
2
CorS
2
c)dataline.
shiftclock.sclksignalclocksserialdataintodinandoutofdoutduring
theframe-syncinterval.whenconfiguredasanoutput(m/shigh),sclkis
generatedinternallybymultiplyingtheframe-syncsignalfrequencyby16
sclk2828i/o
andthenumberofcodecsincascadeinstandardandcontinuousmode.
whenconfiguredasaninput(m/慢),sclkisgeneratedexternallyand
mustbesynchronouswiththemasterclockandframesync.
DVDD2929IDigitalpowersupply
DVSS3030IDigitalground
nc–13,14,15noconnection
4
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