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t
WR
t
DS
t
DH
t
LWD
t
LDAC
t
RST
WR
数据
LDAC
RST
APPLICATIONINFORMATION
StabilityCircuit
DAC8820
OPA277
V
DD
V
DD
U2
地
R
OFS
R
FB
V
输出
I
输出
V
REF
V
REF
U1
C1
DAC8820
SBAS358A–AUGUST2005–REVISEDNOVEMBER2005
theoryofoperation(持续)
figure19.dac8820timingdiagram
table1.functionofcontrolinputs
CONTROLINPUTSREGISTEROPERATION
RSTWRLDAC
0xxasynchronousoperation.resettheinputanddacregistertoapredeterminedvalue.thedac8820
isresettoall0s.
100loadtheinputregisterwithall16databits.
111loadthedacregisterwiththecontentsoftheinputregister.
101theinputanddacregisteraretransparent.
1ldacandwraretiedtogetherandprogrammedasapulse.the16databitsareloadedintothe
inputregisteronthefallingedgeofthepulseandthenloadedintotheDACregisterontherising
edgeofthepulse.
110noregisteroperation.
foracurrent-至-电压(v/i)设计,asshowninFigure20,thedac8820currentoutput(i
输出
)andthe
connectionwiththeinvertingnodeoftheopampshouldbeasshortaspossibleandlaidoutaccordingtocorrect
printedcircuitboard(pcb)layoutdesign.foreachcodechangethereisastepfunction.ifthegainbandwidth
产品(gbp)oftheopampislimitedandparasiticcapacitanceisexcessiveattheinvertingnode,thengain
peakingispossible.因此,acompensationcapacitorc1(4pfto20pf,典型值)canbeaddedtothedesignfor
circuitstability,asshowninFigure20.
figure20.gainpeakingpreventioncircuitwithcompensationcapacitor
9