altera 公司 iii
内容
chapter 修订 dates ........................................................................... xi
关于 这个 handbook ............................................................................ xiii
如何 至 联系 altera .......................................................................................................................... xiii
typographic conventions .................................................................................................................... xiii
部分 i. cyclone ii device 家族 数据 薄板
修订 history .................................................................................................................................... 1–1
chapter 1. 介绍
介绍 ............................................................................................................................................ 1–1
低-费用 embedded 处理 解决方案 .................................................................................. 1–1
低-费用 dsp 解决方案 ................................................................................................................. 1–1
特性 ................................................................................................................................................... 1–2
文档 修订 history ................................................................................................................. 1–8
chapter 2. cyclone ii architecture
函数的 描述 .......................................................................................................................... 2–1
逻辑 elements ....................................................................................................................................... 2–2
le 运行 模式 ........................................................................................................................ 2–4
逻辑 排列 blocks ................................................................................................................................ 2–7
lab interconnects ............................................................................................................................ 2–8
lab 控制 信号 ......................................................................................................................... 2–8
multitrack interconnect ..................................................................................................................... 2–10
行 interconnects .......................................................................................................................... 2–10
column interconnects .................................................................................................................... 2–12
设备 routing ............................................................................................................................... 2–15
global 时钟 网络 &放大; 阶段-锁 loops ............................................................................... 2–16
专心致志的 时钟 管脚 ..................................................................................................................... 2–20
双-目的 时钟 管脚 .............................................................................................................. 2–20
global 时钟 网络 ................................................................................................................... 2–21
global 时钟 网络 分发 ............................................................................................ 2–23
PLLs .................................................................................................................................................. 2–25
embedded 记忆 ............................................................................................................................. 2–27
记忆 模式 ............................................................................................................................... 2–30
时钟 模式 .................................................................................................................................... 2–31
m4k routing 接口 .................................................................................................................. 2–31
embedded multipliers ........................................................................................................................ 2–32
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