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TMS320VC5409A
fixed-pointdigitalsignalprocessor
SPRS140F–NOVEMBER2000–REVISEDJANUARY2005
ListofFigures
2-1144-ballggumicrostarbga™(bottomview)..............................................................................10
2-2144-pinpgelow-profilequadflatpack(topview)........................................................................12
3-1tms320vc5409afunctionalblockdiagram.................................................................................17
3-2programanddatamemorymap................................................................................................20
3-3extendedprogrammemorymap...............................................................................................20
3-4processormodestatusregister(pmst).....................................................................................21
3-5softwarewait-stateregister(swwsr)[memory-mappedregister(mmr)address0028h].........................22
3-6softwarewait-statecontrolregister(swcr)[mmraddress002bh]...................................................23
3-7bank-switchingcontrolregister(bscr)[mmraddress0029h]..........................................................24
3-8host-portinterface—nonmultiplexedmode.................................................................................26
3-9hpimemorymap.................................................................................................................27
3-10pincontrolregister(pcr)......................................................................................................28
3-11multichannelcontrolregister2x(mcr2x)....................................................................................29
3-12multichannelcontrolregister1x(mcr1x)....................................................................................29
3-13receivechannelenableregistersbitlayoutforpartitionsatoh.......................................................29
3-14transmitchannelenableregistersbitlayoutforpartitionsatoh.......................................................30
3-15nonconsecutivememoryreadandi/oreadbussequence..............................................................32
3-16consecutivememoryreadbussequence(n=3reads)...................................................................33
3-17memorywriteandi/owritebussequence...................................................................................34
3-18dmatransfermodecontrolregister(dmmcrn)...........................................................................35
3-19dmachannelenablecontrolregister(dmcectl).........................................................................37
3-20on-chipdmamemorymapforprogramspace(dlaxs=0andslaxs=0)..........................................38
3-21on-chipdmamemorymapfordataandiospace(dlaxs=0andslaxs=0)......................................39
3-22dmprecregister................................................................................................................40
3-23general-purposei/ocontrolregister(gpiocr)[mmraddress003ch]................................................43
3-24general-purposei/ostatusregister(gpiosr)[mmraddress003dh].................................................43
3-25deviceidregister(csidr)[mmraddress003eh].........................................................................44
3-26ifrandimr.......................................................................................................................50
5-1testerpinelectronics............................................................................................................55
5-2internaldivide-用-twoclockoptionwithexternalcrystal.................................................................56
5-3externaldivide-用-twoclocktiming..........................................................................................58
5-4multiply-用-oneclocktiming...................................................................................................60
5-5nonconsecutivemodememoryreads.........................................................................................61
5-6consecutivemodememoryreads.............................................................................................62
5-7memorywrite(mstrb=0).....................................................................................................64
5-8paralleli/oportread(iostrb=0)...........................................................................................66
5-9paralleli/oportwrite(iostrb=0)...........................................................................................67
5-10memoryreadwithexternallygeneratedwaitstates.......................................................................69
5-11memorywritewithexternallygeneratedwaitstates.......................................................................69
ListofFigures
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