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TMS320VC5409A
fixed-pointdigitalsignalprocessor
SPRS140F–NOVEMBER2000–REVISEDJANUARY2005
ListofTables
2-1terminalassignments...........................................................................................................11
2-2signaldescriptions...............................................................................................................13
3-1standardon-chipromlayout................................................................................................19
3-2processormodestatusregister(pmst)fielddescriptions...............................................................21
3-3softwarewait-stateregister(swwsr)fielddescriptions................................................................22
3-4softwarewait-statecontrolregister(swcr)fielddescriptions.........................................................23
3-5bank-switchingcontrolregister(bscr)fielddescriptions...............................................................24
3-6busholdercontrolbits..........................................................................................................25
3-7samplerategeneratorclocksourceselection.............................................................................28
3-8receivechannelenableregistersforpartitionsatohfielddescriptions..............................................30
3-9transmitchannelenableregistersforpartitionsatohfielddescriptions.............................................30
3-10clockmodesettingsatreset...................................................................................................31
3-11dmdsectionofthedmmcrnregister........................................................................................36
3-12dmachannelenablecontrolregister(dmcectl)fielddescription....................................................37
3-13dmareloadregisterselection................................................................................................40
3-14dmainterrupts....................................................................................................................41
3-15dmasynchronizationevents....................................................................................................42
3-16dmachannelinterruptselection...............................................................................................42
3-17cpumemory-mappedregisters................................................................................................45
3-18peripheralmemory-mappedregistersforeachdspsubsystem.........................................................45
3-19mcbspcontrolregistersandsubaddresses.................................................................................47
3-20dmasubbankaddressedregisters...........................................................................................48
3-21interruptlocationsandpriorities................................................................................................50
5-1inputclockfrequencycharacteristics.........................................................................................56
5-2clockmodepinsettingsforthedivide-用-2andbydivide-用-4clockoptions........................................57
5-3divide-用-2anddivide-用-4clockoptionstimingrequirements........................................................57
5-4divide-用-2anddivide-用-4clockoptionsswitchingcharacteristics....................................................57
5-5multiply-用-nclockoptiontimingrequirements............................................................................59
5-6multiply-用-nclockoptionswitchingcharacteristics.......................................................................59
5-7memoryreadtimingrequirements...........................................................................................60
5-8memoryreadswitchingcharacteristics.......................................................................................60
5-9memorywriteswitchingcharacteristics.......................................................................................63
5-10i/oreadtimingrequirements.................................................................................................65
5-11i/oreadswitchingcharacteristics.............................................................................................65
5-12i/owriteswitchingcharacteristics.............................................................................................67
5-13readytimingrequirementsforexternallygeneratedwaitstates.......................................................68
5-14readyswitchingcharacteristicsforexternallygeneratedwaitstates...................................................68
5-15holdandholdatimingrequirements.....................................................................................71
5-16holdandholdaswitchingcharacteristics.................................................................................71
ListofTables
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