www.德州仪器.com
2.2cpu(dspcore)描述
TMS320DM642
video/imagingfixed-pointdigitalsignalprocessor
SPRS200J–JULY2002–REVISEDAUGUST2005
thecpufetchesvelociti™advancedvery-longinstructionwords(vliws)(256bitswide)tosupplyupto
eight32-bitinstructionstotheeightfunctionalunitsduringeveryclockcycle.thevelociti™vliw
architecturefeaturescontrolsbywhichalleightunitsdonothavetobesuppliedwithinstructionsifthey
arenotreadytoexecute.thefirstbitofevery32-bitinstructiondeterminesifthenextinstructionbelongs
tothesameexecutepacketasthepreviousinstruction,orwhetheritshouldbeexecutedinthefollowing
clockasapartofthenextexecutepacket.fetchpacketsarealways256bitswide;不管怎样,theexecute
packetscanvaryinsize.thevariable-lengthexecutepacketsareakeymemory-savingfeature,
distinguishingthec64xcpusfromothervliwarchitectures.thec64x™velociti.2™extensionsadd
enhancementstothetms320c62x™dspvelociti™architecture.theseenhancementsinclude:
•
Registerfileenhancements
•
Datapathextensions
•
quad8-bitanddual16-bitextensionswithdataflowenhancements
•
Additionalfunctionalunithardware
•
Increasedorthogonalityoftheinstructionset
•
Additionalinstructionsthatreducecodesizeandincreaseregisterflexibility
thecpufeaturestwosetsoffunctionalunits.eachsetcontainsfourunitsandaregisterfile.oneset
containsfunctionalunits.l1,.s1,.m1,和.d1;theothersetcontainsunits.d2,.m2,.s2,and.l2.the
tworegisterfileseachcontain3232-bitregistersforatotalof64general-purposeregisters.inadditionto
supportingthepacked16-bitand32-/40-bitfixed-pointdatatypesfoundinthec62x™velociti™vliw
architecture,thec64x™registerfilesalsosupportpacked8-bitdataand64-bitfixed-pointdatatypes.这
twosetsoffunctionalunits,alongwithtworegisterfiles,composesidesaandbofthecpu[seethe
functionalblockandcpu(dspcore)图解,和figure2-1].thefourfunctionalunitsoneachsideof
thecpucanfreelysharethe32registersbelongingtothatside.additionally,eachsidefeaturesa"数据
crosspath"—asingledatabusconnectedtoalltheregistersontheotherside,bywhichthetwosetsof
functionalunitscanaccessdatafromtheregisterfilesontheoppositeside.thec64xcpupipelines
数据-交叉-pathaccessesovermultipleclockcycles.thisallowsthesameregistertobeusedasa
数据-交叉-pathoperandbymultiplefunctionalunitsinthesameexecutepacket.allfunctionalunitsinthe
c64xcpucanaccessoperandsviathedatacrosspath.registeraccessbyfunctionalunitsonthesame
sideofthecpuastheregisterfilecanservicealltheunitsinasingleclockcycle.onthec64xcpu,一个
delayclockisintroducedwheneveraninstructionattemptstoreadaregisterviaadatacrosspathifthat
registerwasupdatedinthepreviousclockcycle.
inadditiontothec62x™dspfixed-pointinstructions,thec64x™dspincludesacomprehensive
collectionofquad8-bitanddual16-bitinstructionsetextensions.thesevelociti.2™extensionsallowthe
C64xCPUtooperatedirectlyonpackeddatatostreamlinedataflowandincreaseinstructionset
效率.thisisakeyfactorforvideoandimagingapplications.
anotherkeyfeatureofthec64xcpuistheload/storearchitecture,whereallinstructionsoperateon
寄存器(asopposedtodatainmemory).twosetsofdata-addressingunits(.d1and.d2)是
responsibleforalldatatransfersbetweentheregisterfilesandthememory.thedataaddressdrivenby
这.dunitsallowsdataaddressesgeneratedfromoneregisterfiletobeusedtoloadorstoredatatoor
fromtheotherregisterfile.thec64x.dunitscanloadandstorebytes(8bits),half-words(16bits),和
words(32bits)withasingleinstruction.andwiththenewdatapathextensions,thec64x.dunitcanload
andstoredoublewords(64bits)withasingleinstruction.此外,thenon-alignedloadandstore
instructionsallowthe.dunitstoaccesswordsanddoublewordsonanybyteboundary.thec64xcpu
supportsavarietyofindirectaddressingmodesusingeitherlinear-orcircular-addressingwith5-or15-位
补偿.allinstructionsareconditional,andmostcanaccessanyoneofthe64registers.someregisters,
不管怎样,aresingledouttosupportspecificaddressingmodesortoholdtheconditionforconditional
说明(iftheconditionisnotautomatically"真实").
DeviceOverview
7
: 点此下载
