EP1S30B1508C5ES_集成电路资料查询网

chapter 修订 dates ..........................................................................vii

关于这个 handbook .............................................................................. ix

如何至 find 信息 ........................................................................................................................ ix

如何至联系 altera ............................................................................................................................. ix

typographic conventions ........................................................................................................................ x

部分 i. stratix de恶行家族数据薄板

修订 history ............................................................................................................................ 部分 i–1

chapter 1. 介绍

介绍 ............................................................................................................................................ 1–1

特性 ................................................................................................................................................... 1–2

chapter 2. stratix architecture

函数的描述 .......................................................................................................................... 2–1

逻辑排列 blocks ................................................................................................................................ 2–3

lab interconnects ............................................................................................................................ 2–4

lab 控制信号 ......................................................................................................................... 2–5

逻辑 elements ....................................................................................................................................... 2–6

lut chain &放大; 寄存器 chain .......................................................................................................... 2–8

addnsub 信号 ................................................................................................................................. 2–8

le 运行模式 ........................................................................................................................ 2–8

clear &放大; preset 逻辑控制 ........................................................................................................ 2–13

multitrack interconnect ..................................................................................................................... 2–14

trimatrix 记忆 ............................................................................................................................... 2–21

记忆模式 ............................................................................................................................... 2–22

clear 信号 .................................................................................................................................... 2–24

parity 位支持 ........................................................................................................................... 2–24

变换寄存器支持 .................................................................................................................... 2–25

记忆块大小 ......................................................................................................................... 2–26

独立时钟模式 .............................................................................................................. 2–44

输入/输出时钟模式 ........................................................................................................... 2–46

读/写时钟模式 ............................................................................................................... 2–49

单独的-端口模式 ............................................................................................................................ 2–51

乘法器块 .............................................................................................................................. 2–57

adder/输出 blocks ................................................................................................................... 2–61

模式的运作 ....................................................................................................................... 2–64

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altera 公司 iii 内容 chapter 修订 dates ..........................................................................vii 关于这个 handbook .............................................................................. ix 如何至 find 信息 ........................................................................................................................ ix 如何至联系 altera ............................................................................................................................. ix typographic conventions ........................................................................................................................ x 部分 i. stratix de恶行家族数据薄板修订 history ............................................................................................................................ 部分 i–1 chapter 1. 介绍介绍 ............................................................................................................................................ 1–1 特性 ................................................................................................................................................... 1–2 chapter 2. stratix architecture 函数的描述 .......................................................................................................................... 2–1 逻辑排列 blocks ................................................................................................................................ 2–3 lab interconnects ............................................................................................................................ 2–4 lab 控制信号 ......................................................................................................................... 2–5 逻辑 elements ....................................................................................................................................... 2–6 lut chain &放大; 寄存器 chain .......................................................................................................... 2–8 addnsub 信号 ................................................................................................................................. 2–8 le 运行模式 ........................................................................................................................ 2–8 clear &放大; preset 逻辑控制 ........................................................................................................ 2–13 multitrack interconnect ..................................................................................................................... 2–14 trimatrix 记忆 ............................................................................................................................... 2–21 记忆模式 ............................................................................................................................... 2–22 clear 信号 .................................................................................................................................... 2–24 parity 位支持 ........................................................................................................................... 2–24 变换寄存器支持 .................................................................................................................... 2–25 记忆块大小 ......................................................................................................................... 2–26 独立时钟模式 .............................................................................................................. 2–44 输入/输出时钟模式 ........................................................................................................... 2–46 读/写时钟模式 ............................................................................................................... 2–49 单独的-端口模式 ............................................................................................................................ 2–51 乘法器块 .............................................................................................................................. 2–57 adder/输出 blocks ................................................................................................................... 2–61 模式的运作 ....................................................................................................................... 2–64

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