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TIMINGCHARACTERISTICS
(1)(2)
SCLK
同步
SDIN
D15 D14 D13
D12
D11 D1 D0 D15
t
8
t
4
t
3
t
2
t
1
t
7
t
6
t
5
D0
t
9
输入 文字 n 输入 文字 n+1
未阐明的
D15 D14
D0
输入 文字 n
t
10
SDO
CLR
DAC7551
SLAS441–MARCH2005
V
DD
=2.7vto5.5v,r
L
=2k
Ω
tognd;allspecifications–40°cto105°c,unlessotherwisespecified
PARAMETERTESTCONDITIONSMINTYPMAXUNITS
V
DD
=2.7vto3.6v20
t
1
(3)
SCLKcycletimens
V
DD
=3.6vto5.5v20
V
DD
=2.7vto3.6v10
t
2
SCLKHIGHtimens
V
DD
=3.6vto5.5v10
V
DD
=2.7vto3.6v10
t
3
SCLKLOWtimens
V
DD
=3.6vto5.5v10
V
DD
=2.7vto3.6v4
SYNCfallingedgetoSCLKfallingedgesetup
t
4
ns
时间
V
DD
=3.6vto5.5v4
V
DD
=2.7vto3.6v5
t
5
Datasetuptimens
V
DD
=3.6vto5.5v5
V
DD
=2.7vto3.6v4.5
t
6
Dataholdtimens
V
DD
=3.6vto5.5v4.5
V
DD
=2.7vto3.6v0
t
7
SCLKfallingedgetoSYNCrisingedgens
V
DD
=3.6vto5.5v0
V
DD
=2.7vto3.6v20
t
8
MinimumSYNCHIGHtimens
V
DD
=3.6vto5.5v20
V
DD
=2.7vto3.6vtbd
t
9
SCLKfallingedgetoSDOvalidns
V
DD
=3.6vto5.5vtbd
V
DD
=2.7vto3.6vtbd
t
10
CLRpulsewidthlowns
V
DD
=3.6vto5.5vtbd
(1)allinputsignalsarespecifiedwitht
R
=t
F
=1ns(10%to90%ofv
DD
)andtimedfromavoltagelevelof(v
IL
+V
IH
)/2.
(2)seeserialwriteoperationtimingdiagramFigure1.
(3)maximumsclkfrequencyis50mhzatv
DD
=2.7vto5.5v.
figure1.serialwriteoperation
5