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1.2description
TMS320DM642
video/imagingfixed-pointdigitalsignalprocessor
SPRS200J–JULY2002–REVISEDAUGUST2005
thetms320c64x™dsps(includingthetms320dm642device)arethehighest-performancefixed-要点
dspgenerationinthetms320c6000™dspplatform.thetms320dm642(dm642)deviceisbasedon
thesecond-generationhigh-效能,advancedvelociti™very-长-操作指南-文字(vliw)architec-
ture(velociti.2™)developedbytexasinstruments(德州仪器),makingthesedspsanexcellentchoicefor
digitalmediaapplications.thec64x™isacode-compatiblememberofthec6000™dspplatform.
withperformanceofupto5760millioninstructionspersecond(mips)ataclockrateof720mhz,这
dm642deviceofferscost-effectivesolutionstohigh-performancedspprogrammingchallenges.这
dm642dsppossessestheoperationalflexibilityofhigh-speedcontrollersandthenumericalcapabilityof
arrayprocessors.thec64x™dspcoreprocessorhas64general-purposeregistersof32-bitwordlength
andeighthighlyindependentfunctionalunits—twomultipliersfora32-bitresultandsixarithmeticlogic
单位(alus)—withvelociti.2™extensions.thevelociti.2™extensionsintheeightfunctionalunits
includenewinstructionstoacceleratetheperformanceinvideoandimagingapplicationsandextendthe
parallelismofthevelociti™architecture.thedm642canproducefour16-bitmultiply-accumulates
(macs)percycleforatotalof2880millionmacspersecond(mmacs),oreight8-bitmacspercyclefor
atotalof5760mmacs.thedm642dspalsohasapplication-specifichardwarelogic,在-chipmemory,
andadditionalon-chipperipheralssimilartotheotherc6000™dspplatformdevices.
thedm642usesatwo-levelcache-basedarchitectureandhasapowerfulanddiversesetofperipherals.
thelevel1programcache(l1p)isa128-kbitdirectmappedcacheandthelevel1datacache(l1d)是
a128-kbit2-wayset-associativecache.thelevel2memory/cache(l2)consistsofan2-mbitmemory
spacethatissharedbetweenprogramanddataspace.l2memorycanbeconfiguredasmapped
记忆,cache,orcombinationsofthetwo.theperipheralsetincludes:threeconfigurablevideoports;一个
10/100mb/sethernetmac(emac);amanagementdatainput/输出(mdio)单元;avcxo
interpolatedcontrolport(vic);onemultichannelbufferedaudioserialport(mcasp0);aninter-整体的
电路(i2c)busmodule;twomultichannelbufferedserialports(mcbsps);three32-bitgeneral-目的
计时器;auser-configurable16-bitor32-bithost-portinterface(hpi16/hpi32);aperipheralcomponent
interconnect(pci);a16-pingeneral-purposeinput/outputport(gp0)withprogrammableinterrupt/事件
generationmodes;anda64-bitgluelessexternalmemoryinterface(emifa),whichiscapableof
interfacingtosynchronousandasynchronousmemoriesandperipherals.
thedm642devicehasthreeconfigurablevideoportperipherals(vp0,vp1,andvp2).thesevideoport
peripheralsprovideagluelessinterfacetocommonvideodecoderandencoderdevices.thedm642
videoportperipheralssupportmultipleresolutionsandvideostandards(e.g.,ccir601,itu-bt.656,
bt.1120,smpte125m,260m,274m,and296m).
thesethreevideoportperipheralsareconfigurableandcansupporteithervideocaptureand/orvideo
displaymodes.eachvideoportconsistsoftwochannels—aandbwitha5120-bytecapture/显示
bufferthatissplittablebetweenthetwochannels.
formoredetailsonthevideoportperipherals,seethe
tms320c64xdspvideoport/vcxointerpolated
控制(vic)portreferenceguide
(literaturenumberspru629).
themcasp0portsupportsonetransmitandonereceiveclockzone,witheightserialdatapinswhichcan
beindividuallyallocatedtoanyofthetwozones.theserialportsupportstime-divisionmultiplexingon
eachpinfrom2to32timeslots.thedm642hassufficientbandwidthtosupportall8serialdatapins
transmittinga192-khzstereosignal.serialdataineachzonemaybetransmittedandreceivedon
multipleserialdatapinssimultaneouslyandformattedinamultitudeofvariationsonthephilipsinter-ic
声音(i
2
s)format.
inaddition,themcasp0transmittermaybeprogrammedtooutputmultiples/pdif,iec60958,aes-3,
cp-430encodeddatachannelssimultaneously,withasingleramcontainingthefullimplementationof
userdataandchannelstatusfields.
mcasp0alsoprovidesextensiveerror-checkingandrecoveryfeatures,suchasthebadclockdetection
circuitforeachhigh-frequencymasterclockwhichverifiesthatthemasterclockiswithinaprogrammed
frequencyrange
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tms320dm642video/imagingfixed-pointdigitalsignalprocessor
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