pci 9080T一个ble 的 内容
PLXTechnology, inc., 1997页viiiVersion1.01
4.6.7(dMapadr1; pci:98h, loc:118h) dM一个 channel1 pci address reg是ter.....................................................................81
4.6.8(dMaladr1; pci:9ch, loc:11ch)DM一个 频道1local address reg是ter.................................................................81
4.6.9(dMasiz1; pci:a0h,loc:120h)DM一个 频道 1Transfer 大小 (bytes) reg是ter...........................................................81
4.6.10(dMadpr1; pci:a4h, loc:124h) dM一个 频道1Descript或者 pointerRegister..............................................................81
4.6.11(dMacsr0; pci:a8h, loc:128h) dM一个 频道0Command/stat美国 register...............................................................82
4.6.12(dMacsr1; pci:a9h, loc:129h) dM一个 频道1Command/stat美国 register...............................................................82
4.6.13(dMaarb; pci:ach, loc:12ch) dM一个 arbitrationRegister.............................................................................................82
4.6.14(dMathr; pci:b0h, loc:130h) dM一个Threshold reg是ter..............................................................................................83
4.7messaging qUEUEREGISTERS.......................................................................................................................84
4.7.1(oplfis; pci:30h, loc:b0) outbound postL是t先进先出 在terruptStat美国 register.............................................................84
4.7.2(oplfiM; pci:34h, loc:b4) outboundPostList fIfo interruptMask register..............................................................84
4.7.3(iqp; pci:40h)Inbound queuePort reg是ter...................................................................................................................84
4.7.4(oqp; pci:44h) outbound queuePort reg是ter..............................................................................................................85
4.7.5(mqcr; pci:c0h, loc:140h)Mess一个ging queue configur一个tionRegister........................................................................85
4.7.6(qbar; pci:c4h, loc:144h) queue 根基 一个ddress reg是ter..........................................................................................85
4.7.7(ifhpr; pci:c8h, loc:148h)Inbound自由HeadPointer register................................................................................86
4.7.8(如果Tpr; pci:cch, loc:14ch) inbound freeTail pointer register..................................................................................86
4.7.9(iphpr; pci:d0h, loc:150h)InboundPost head po在ter register................................................................................86
4.7.10(ipTpr; pci:d4h, loc:154h)在bound邮递Tail pointerRegister....................................................................................86
4.7.11(ofhpr; pci:d8h, loc:158h) 输出boundFreehead po在ter reg是ter............................................................................87
4.7.12(的Tpr; pci:dch, loc:15ch) outbound freeTailPointer reg是ter..............................................................................87
4.7.13(ophpr; pci:e0h, loc:160h) 输出boundPostHeadPointer reg是ter............................................................................87
4.7.14(运算Tpr; pci:e4h, loc:164h) outbound postTailPointer register...............................................................................87
4.7.15(qsr; pci:e8h, loc:168h) queue st一个tus/control reg是ter............................................................................................88
5.管脚DESCRIPTION........................................................................................................................................................89
5.1管脚 suM毫安RY.......................................................................................................................................................89
5.2管脚 输出 一般To alLBUs moDES............................................................................................................90
5.3c bUs moDE管脚 ouT..........................................................................................................................................94
5.4j buS模式 管脚 ouT...........................................................................................................................................96
5.5S总线 模式 管脚OUT..........................................................................................................................................98
6.ELECTRIC一个l specifiC一个Tions................................................................................................................................100
7.包装, 信号, 和管脚 输出 规格............................................................................................................103
7.1PACkage mecH一个ICALDIMENSIONS............................................................................................................103
7.2TYPICal pci bUSMASTer 一个DAPTER..............................................................................................................104
7.39080 管脚 输出 (s, j, 和 c moDES)..................................................................................................................105
: 点此下载
