www.德州仪器.com
Biases
和
References
Startup
保护
逻辑
VREGok
RINP
RINN
Ramp
发生器
ROSC
VCCok
4v reg
AVCC
VREG
PWM
逻辑
增益
控制
增益
控制
LINP
LINN
关闭
VBYP
VBYP
mstr/slv
PWM
逻辑
同步
AVCC
AVCC
AVCC
增益
控制
GAIN0
GAIN1
8
至 增益 adj.
blocks 和
startup 逻辑
沉默的
故障
VREG
AGND
VBYP
VBYP
VREG
VBYP
VClamp
Gen
PVCCR
门
驱动
门
驱动
VClamp
Gen
门
驱动
热的
SC
发现
PVCCR
门
驱动
BSLN
VCLAMPL
PVCCL
PVCCL
BSLP
LOUTN
BSRN
VCLAMPR
PVCCR
PVCCR
ROUTN
BSRP
ROUTP
PGNDR
PVCCL
PVCCL
PGNDL
LOUTP
增益
增益
增益
增益
TLL 输入
缓存区
(vcc 一致的)
TLL 输入
缓存区
(vcc 一致的)
TYPICALCHARACTERISTICS
TPA3100D2
SLOS469B–OCTOBER2005–REVISEDOCTOBER2005
FUNCTIONALBLOCKDIAGRAM
TABLEOFGRAPHS
(1)
图示
thd+ntotalharmonicdistortion+noisevsfrequency1,2,3,4
thd+ntotalharmonicdistortion+noisevsoutputpower5,6,7,8
关闭-loopresponsevsfrequency9,10
outputpowervssupplyvoltage11.12
efficiencyvsoutputpower13,14
V
CC
supplycurrentvstotaloutputpower15,16
crosstalkvsfrequency17,18
k
SVR
supplyripplerejectionratiovsfrequency19,20
(1)allgraphsweremeasuredusingthetpa3100d2evm.
7
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