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TMS320VC5410A
fixed-pointdigitalsignalprocessor
SPRS139G–NOVEMBER2000–REVISEDJANUARY2005
ListofFigures
2-1144-ballggumicrostarbga™(bottomview)..............................................................................10
2-2144-pinpgelow-profilequadflatpack(topview)........................................................................12
3-1tms320vc5410afunctionalblockdiagram.................................................................................17
3-2programanddatamemorymap................................................................................................20
3-3extendedprogrammemorymap...............................................................................................21
3-4processormodestatusregister(pmst).....................................................................................21
3-5softwarewait-stateregister(swwsr)[memory-mappedregister(mmr)address0028h].........................23
3-6softwarewait-statecontrolregister(swcr)[mmraddress002bh]...................................................24
3-7bank-switchingcontrolregister(bscr)[mmraddress0029h]..........................................................24
3-8host-portinterface—nonmultiplexedmode.................................................................................27
3-9hpimemorymap.................................................................................................................28
3-10pincontrolregister(pcr)......................................................................................................29
3-11multichannelcontrolregister2x(mcr2x)....................................................................................30
3-12multichannelcontrolregister1x(mcr1x)....................................................................................31
3-13receivechannelenableregistersbitlayoutforpartitionsatoh.......................................................31
3-14transmitchannelenableregistersbitlayoutforpartitionsatoh.......................................................31
3-15nonconsecutivememoryreadandi/oreadbussequence..............................................................34
3-16consecutivememoryreadbussequence(n=3reads)...................................................................35
3-17memorywriteandi/owritebussequence...................................................................................36
3-18dmatransfermodecontrolregister(dmmcrn)...........................................................................37
3-19dmachannelenablecontrolregister(dmcectl).........................................................................39
3-20on-chipdmamemorymapforprogramspace(dlaxs=0andslaxs=0)..........................................40
3-21on-chipdmamemorymapfordataandiospace(dlaxs=0andslaxs=0)......................................41
3-22dmprecregister................................................................................................................42
3-23general-purposei/ocontrolregister(gpiocr)[mmraddress003ch]................................................45
3-24general-purposei/ostatusregister(gpiosr)[mmraddress003dh].................................................45
3-25deviceidregister(csidr)[mmraddress003eh].........................................................................46
3-26ifrandimr.......................................................................................................................52
5-1testerpinelectronics............................................................................................................57
5-2internaldivide-用-twoclockoptionwithexternalcrystal.................................................................58
5-3externaldivide-用-twoclocktiming..........................................................................................60
5-4multiply-用-oneclocktiming...................................................................................................62
5-5nonconsecutivemodememoryreads.........................................................................................63
5-6consecutivemodememoryreads.............................................................................................64
5-7memorywrite(mstrb=0).....................................................................................................66
5-8paralleli/oportread(iostrb=0)...........................................................................................68
5-9paralleli/oportwrite(iostrb=0)...........................................................................................69
5-10memoryreadwithexternallygeneratedwaitstates.......................................................................71
5-11memorywritewithexternallygeneratedwaitstates.......................................................................71
ListofFigures
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