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TMS320VC5410A
fixed-pointdigitalsignalprocessor
SPRS139G–NOVEMBER2000–REVISEDJANUARY2005
ListofTables
2-1terminalassignments...........................................................................................................11
2-2signaldescriptions...............................................................................................................13
3-1standardon-chipromlayout................................................................................................19
3-2processormodestatusregister(pmst)fielddescriptions...............................................................22
3-3softwarewait-stateregister(swwsr)fielddescriptions................................................................23
3-4softwarewait-statecontrolregister(swcr)fielddescriptions.........................................................24
3-5bank-switchingcontrolregister(bscr)fielddescriptions...............................................................25
3-6busholdercontrolbits..........................................................................................................26
3-7samplerategeneratorclocksourceselection.............................................................................30
3-8receivechannelenableregistersforpartitionsatohfielddescriptions..............................................31
3-9transmitchannelenableregistersforpartitionsatohfielddescriptions.............................................31
3-10clockmodesettingsatreset...................................................................................................33
3-11dmdsectionofthedmmcrnregister........................................................................................38
3-12dmachannelenablecontrolregister(dmcectl)fielddescriptions..................................................39
3-13dmareloadregisterselection................................................................................................42
3-14dmainterrupts....................................................................................................................43
3-15dmasynchronizationevents....................................................................................................44
3-16dmachannelinterruptselection...............................................................................................44
3-17cpumemory-mappedregisters................................................................................................47
3-18peripheralmemory-mappedregistersforeachdspsubsystem.........................................................48
3-19mcbspcontrolregistersandsubaddresses.................................................................................49
3-20dmasubbankaddressedregisters...........................................................................................50
3-21interruptlocationsandpriorities................................................................................................52
5-1inputclockfrequencycharacteristics.........................................................................................58
5-2clockmodepinsettingsforthedivide-用-2andbydivide-用-4clockoptions........................................59
5-3divide-用-2anddivide-用-4clockoptionstimingrequirements........................................................59
5-4divide-用-2anddivide-用-4clockoptionsswitchingcharacteristics....................................................59
5-5multiply-用-nclockoptiontimingrequirements............................................................................61
5-6multiply-用-nclockoptionswitchingcharacteristics.......................................................................61
5-7memoryreadtimingrequirements...........................................................................................62
5-8memoryreadswitchingcharacteristics.......................................................................................62
5-9memorywriteswitchingcharacteristics.......................................................................................65
5-10i/oreadtimingrequirements.................................................................................................67
5-11i/oreadswitchingcharacteristics.............................................................................................67
5-12i/owriteswitchingcharacteristics.............................................................................................69
5-13readytimingrequirementsforexternallygeneratedwaitstates.......................................................70
5-14readyswitchingcharacteristicsforexternallygeneratedwaitstates...................................................70
5-15holdandholdatimingrequirements.....................................................................................73
5-16holdandholdaswitchingcharacteristics.................................................................................73
ListofTables
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