BS62LV256
r0201-bS62LV256
Revisi在 2.5
M一个y.2006
7
WRITECYCLE2
(1,6)
NOTES:
1.WEmust是highduringaddresstransitions.
2.Theinternalwritetimeofthemem或者yisdefinedbytheoverlapofCE和WElow.一个llsignals
mustbe一个ctivetoiniti一个te一个write一个nd一个y一个signalc一个nterminate一个writebygoingin一个ctive.The
dat一个inputset向上和holdtimingshould是referencedtothesecondtransiti在边缘ofthe
signalthattermin一个testhewrite.
3.t
WR
isme一个suredfromtheearlierofCEorWEgoinghigh一个tthe终止ofwritecycle.
4.Duringthis每iod,DQpins是intheoutputst一个tesothattheinputsignalsofoppositephaseto
theoutputsmust非tbeapplied.
5.如果theCElowtransiti在occurssimultaneouslywiththeWElowtransitions或者一个ftertheWE
transiti在,outputrem一个inin一个highimpedancest一个te.
6.OEisc在tinuouslylow(OE=V
IL
).
7.D
OUT
isthes一个mephaseofwritedat一个ofthiswritecycle.
8.D
OUT
isthereaddat一个ofnextaddress.
9.如果CEislowduringthis每iod,DQpins是intheoutputst一个te.Thenthedat一个inputsignalsof
oppositeph一个setotheoutputsmust非t是appliedtothem.
10.Transiti在isme一个sured
±
500mVfromsteadyst一个tewithC
L
=5pF.
Thepar一个meterisguaranteedbut非t100%tested.
11.t
CW
isme一个suredfromthel一个terofCEgoinglowtotheendofwrite.
t
WC
t
CW
(11)
t
WP
(2)
t
AW
t
WHZ
(4,10)
t
作
t
DH
t
DW
D
在
D
OUT
我们
CE
t
OW
(7) (8)
(8,9)
一个DDRESS
(5)
: 点此下载
