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Table of Contents
Geode™ GXm 处理器
1.0 ArchitectureOverview............................................. 8
1.1 INTEGERUNIT ...........................................................8
1.2 FLOATINGPOINTUNIT ....................................................9
1.3 写-backcacheunit .................................................9
1.4 MEMORYMANAGEMENTUNIT ..............................................9
1.4.1 InternalBusInterfaceUnit ............................................9
1.5 整体的 功能 . . . . .............................................9
1.5.1 Graphics Accelerator . . . .............................................9
1.5.2 DisplayController ..................................................10
1.5.3 XpressRAMMemorySubsystem ......................................10
1.5.4 PCIController.....................................................10
1.6 geodegxm/cs5530systemdesigns ....................................11
2.0 signaldefinitions................................................ 13
2.1 PINASSIGNMENTS ......................................................13
2.2 SIGNALDESCRIPTIONS ..................................................24
2.2.1 SystemInterfaceSignals ............................................24
2.2.2 PCIInterfaceSignals ...............................................26
2.2.3 MemoryControllerInterfaceSignals ...................................29
2.2.4 VideoInterfaceSignals .............................................30
2.2.5 电源,地面,andnoconnectsignals................................32
2.2.6 InternalTestandMeasurementSignals ................................32
2.3 SUBSYSTEMSIGNALCONNECTIONS .......................................34
2.4 POWERPLANES .........................................................36
3.0 ProcessorProgramming .......................................... 38
3.1 COREPROCESSORINITIALIZATION........................................38
3.2 instructionsetoverview.............................................39
3.2.1 LockPrefix .......................................................39
3.3 REGISTERSETS.........................................................40
3.3.1 ApplicationRegisterSet.............................................40
3.3.2 SystemRegisterSet ...............................................44
3.3.3 ModelSpecificRegisterSet ..........................................59
3.3.4 TimeStampCounter ...............................................59
3.4 addressspaces.......................................................60
3.4.1 i/oaddressspace .................................................60
3.4.2 MemoryAddressSpace.............................................60
3.5 补偿,段,andpagingmechanisms .............................61
3.6 OFFSETMECHANISM ....................................................61
3.7 DESCRIPTORSANDSEGMENTMECHANISMS................................62
3.7.1 Real 和 模拟的 8086 模式 段 Mechanisms . . . . . . . . ...............62
3.7.2 SegmentMechanisminProtectiveMode................................63
3.7.3 GDTRandLDTRRegisters ..........................................66
3.7.4 DescriptorBitStructure .............................................67
3.7.5 GateDescriptors ..................................................69
3.8 multitaskingandtaskstatesegments................................70
3.9 PAGINGMECHANISM.....................................................72
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